An Electrically Erasable and Programmable ROM (EEPROM) can electrically erase and write data by using an electric signal while it is mounted on a circuit board. Therefore, it is more useful than an EPROM of the ultraviolet erase type. Demand for EEPROMs is, therefore, rapidly increasing for use with control circuits, IC cards (memory cards), and the like. In order to produce an EEPROM having a large capacity in particular, its memory cell has the structure such as shown in FIGS. 7A to 7C.
FIG. 7A is a plan view showing a pattern layout, FIG. 7B is a cross sectional view taken along line B--B of FIG. 7A, and FIG. 7C is a cross sectional view taken along line C--C of FIG. 7A. In these figures, reference numeral 11 represents a floating gate made of a polysilicon first layer. Reference numeral 12 represents an erase gate made of a polysilicon second layer. Reference numeral 13 represents a control gate made of a polysilicon third layer. The control gate 13 is also used as a word line. Reference numeral 14 represents a P-type substrate. Reference numerals 15 and 16 represent a source and a drain made of an N.sup.+ -type diffusion layer and formed on the substrate 14, respectively. Reference numeral 17 represents a contact hole. Reference numeral 18 represents a data line made of an aluminum layer connected to the drain 16 via the contact hole 17. Reference numeral 19 represents a gate insulating film at the floating gate transistor region having a thickness of 300 angstroms. Reference numeral 20 represents a gate insulating film having a thickness of 350 angstroms and formed between the floating gate 11 and the erase gate 12. Reference numeral 21 represents a gate insulating film formed between the floating gate 11 and the control gate 13. This gate insulating film 21 is made of a three-layer structure film having an Oxide-Nitride-Oxide (O--N--O) structure. Reference numeral 22 represents a gate insulating film formed between the erase gate 12 and the control gate 13 and also having the O--N--O structure. Reference numeral 23 represents a gate insulating film at a select transistor region which uses the polysilicon layer 13 as its gate electrode. Reference numeral 24 represents a field insulating film, and 25 represents an interlayer insulating film.
The equivalent circuit of the memory cell shown in FIGS. 7A to 7C is shown in FIG. 8, and the equivalent circuit of the capacitance system is shown in FIG. 9. In FIG. 8, V.sub.D represents a drain potential, V.sub.s a source potential, V.sub.FG a floating gate potential, V.sub.EG an erase gate potential, and VCG a control gate potential. In FIG. 9, C.sub.FC represents a capacitance between the floating gate 11 and the control gate 13, C.sub.FE a capacitance between the floating gate 11 and the erase gate 12, C.sub.FD a capacitance between the floating gate 11 and the drain 16, and C.sub.FS another capacitance as viewed from the floating gate 11. In this capacitance system, the initial value Q.sub.(I) of electrical charge stored in all capacitors is given by the following equation. EQU Q.sub.(I) =(V.sub.FG -V.sub.CG)C.sub.FC +(V.sub.FG -V.sub.EG)C.sub.FE +(V.sub.FG -V.sub.D)C.sub.FD +(V.sub.FG -V.sub.S)C.sub.FS ( 1)
The total capacitance C.sub.T is given by the following equation. EQU C.sub.T =C.sub.FC +C.sub.FE +C.sub.FD +C.sub.FS ( 2)
The voltage VFG applied to the floating gate is therefore given by the following equation. EQU V.sub.FG ={(V.sub.CG C.sub.FC +V.sub.EG C.sub.FE +V.sub.D C.sub.FD +V.sub.S C.sub.FS)/C.sub.T }+{Q.sub.(I) /C.sub.T } (3)
By substituting Q.sub.(i) /C.sub.T =V.sub.FG(i) and V.sub.S =0 V into the equation (3), we obtain EQU V.sub.FG ={(V.sub.CG C.sub.FC +V.sub.EG C.sub.FE +V.sub.D C.sub.FD)/C.sub.T }+V.sub.FG(I) ( 4)
Memory cells, each constructed as above, are actually disposed in a matrix within a memory cell array, referred to hereafter as a memory cell array block or as a block. For simplicity of description, a four bit memory array having four memory cells M1 to M4 is shown in FIG. 10. Each of the drains 16 of the four memory cells M1 to M4 is connected to two data lines DL1 and DL2. Each of the control gates 13 is connected to two word lines WL1 and WL2. The erase gates 12 are commonly connected to one erase line EL, and the sources are applied with a reference voltage (e.g., 0 V).
In the memory cell array constructed as above, data is erased collectively for all the memory cells M1 to M4. More in particular, the source potential V.sub.S, drain potential V.sub.D, and control gate potential V.sub.CG of each memory cell are set to 0 V (namely, the data lines DL1 and DL2, and word lines WL1 and WL2 are set to 0 V), and the erase gate potential V.sub.EG is set to a high potential (e.g., +20 V). In this case, by the Fowler-Nordheim tunnel effect, electrons in the floating gate 11 are emitted to the erase gate 12 by the electric field so that the floating gate 11 is charged positive. Assuming that the potential V.sub.FG (i) Of the floating gate 11 rises for example to +3 V (assuming in this case the threshold voltage V.sub.TH of the floating gate transistor is 1 V), then an inversion layer is formed under the floating gate 11 so that the threshold voltages of the memory cells M1 to M4 become lower. This state assumes that data " 1" is being stored.
Consider next writing data in a selected memory cell, e.g., memory cell M1 in the memory cell array. In order to write data in the selected memory cell M1, the control gate potential V.sub.CG (potential at the word line WL1) for the selected memory cell M1 is set to a high potential, e.g., +12.5 V, the drain potential V.sub.D (potential at the data line DL1) is set to a high potential, e.g., +10 V, and the source voltage V.sub.S, and potentials at the data line DL2 and word line WL2 are set to 0 V. The erase gate potential VFG is set to +5 V for example so that the potential at the floating gate 11 rises to alleviate writing data into the selected cell M1. The hot electron effect occurs near the drain 16 of the selected cell M1 so that electrons generated by impact ionization are injected into the floating gate 11. With the control gate potential V.sub.CG of 12.5 V, the floating gate potential V.sub.FG will become 10.5 V according to the equation (4). However, the potential at the erase gate 12 as seen from the floating gate 11 is -5.5 V because the erase gate potential V.sub.EG is 5 V. By applying 5 V to the erase gate 12 as in the above case, the electrical field is relaxed relative to the erase gate at the floating gate of a non-selected cell M2 connected to the same word line as that of the selected cell M1. Accordingly, erroneous operation due to erroneous data writing can be avoided, resulting in improved reliability. Apart from the above discussion, the voltage stress applied between the drain 16 and the floating gate changes greatly with whether the data of a memory cell is "1" or "0". The voltage stresses applied between the drain 16 and the floating gate 11 of each of four memory cells Mi! to M4 are summarized in Table 1.
TABLE 1 __________________________________________________________________________ CELL CELL DATA WL1 WL2 DL1 DL2 V.sub.EG V.sub.FE V.sub.D -V.sub.FG MODE __________________________________________________________________________ M1 "1" 12.5 V 10 V 5 V -- -- DATA WRITE "0" M2 "1" 12.5 V 0 V 5 V 10.5 V -10.5 V POSSIBLE WRITE ERROR "0" 4.5 V -4.5 V -- M3 "1" 0 V 10 V 5 V 3.0 V 7.0 V -- "0" -3.0 V 13.0 V POSSIBLE ERASE ERROR M4 "1" 0 V 0 V 5 V 3.0 V -3.0 V -- "0" -3.0 V 3.0 V -- __________________________________________________________________________
The maximum voltage stress to the floating gate among non-selected memory cells M2 to M4 in FIG. 10 is applied to the non-selected memory cell M3 when it has data "0", the control gate thereof being connected to the word line WL2 different from the word line WL1 of the selected memory cell M1. Specifically, as seen from Table 1, a voltage of +13.0 V is applied between the floating gate 11 and drain 16 of the non-selected cell M3. Electrons in the floating gate 11 are therefore likely to be emitted to the drain, and in some cases there is a fear of erroneously erasing the data. The case second most likely to be operated erroneously, is when the memory cell M2 has data "1". In this case, electrons are likely to be injected into the floating gate, resulting in writing data erroneously.
FIG. 11 is a circuit diagram showing a conventional memory having memory cells described above. In FIG. 11, each of cells 30 in a memory cell array 31 is connected to n data lines DL1 to DLn, and each control gate 13 is connected to m word lines WL1 to WLm. Erase gates 12 of the memory cells 30 are commonly connected to an erase line EL, and a reference voltage, e.g., 0 V is applied to the sources 15. The erase gates of all the memory cells in the memory cell array are commonly connected so that a voltage V.sub.EG is applied to the erase gates of all the memory cells 30 at the same time when data is written. In FIG. 11, reference numeral 32 represents a row decoder, 33 a column decoder, 34-1 to 34-n column select transistors, 35 a bus line, 36 a data input circuit, 37 a sense amplifier circuit, 38 a data output circuit, 39 an erase voltage booster circuit, and 41 an address buffer.
Consider the case where it takes a time t to write data in one cell (one bit) and data is written sequentially for all bits. The maximum time while a stress is applied to a non-selected memory cell becomes (m-1).times.t per one bit (one cell) (for example, the stress time for a non-selected memory cell M3 in the possible erroneous data erase state as described with Table 1, is the time duration while the control gate 13 is applied with 0 V and the drain 16 is applied with 10 V). On the other hand, the maximum time while a stress is applied to a non-selected memory cell becomes (n-1).times.t per one bit (one cell) (for example, the stress time for a non-selected memory cell M2 in the possible erroneous data write state as described with Table 1, is the time duration while the control gate 13 is applied with 12.5 V and the drain 16 is applied with 0 V). As described above, m represents the number of rows, and n represents the number of columns.
For example, for a memory of 1M bits (128K words.times.8 bits), n=128 and m=1024. Assuming that a data write time for one bit is 1 ms, the stress time during the possible erroneous data erase state is given by EQU 1 ms.times.(1024-1)=1.023 second (a)
The stress time during the possible erroneous data write state is given by EQU 1 ms.times.127=127 ms
These stress times pose no practical problem when it is considered that the thickness of the insulating film of the floating gate 111 is 300 angstroms and that the probability of erroneous data erase or write is proportional to the stress time.
FIGS. 12A to 12C show a second example of a conventional EEPROM cell having no erase gate, Like elements to those in FIGS. 7A to 7C are given identical reference numerals. Points of difference from the EEPROM shown in FIGS. 7A to 7C reside in that the EEPROM shown in FIGS. 12A to 12C has no erase gate and no select transistor having the control gate 13 as its gate, and the floating gate 11 is in direct contact with the source 15 and drain 16. The floating gate insulating film 19 is formed as thin as about 100 angstroms.
Next, the operation principle of the EEPROM shown in FIGS. 12A to 12C will be described.
In erasing data, the source 15 is applied with an erase voltage of 10 V, the drain 16 is made to enter a floating state, and the control gate 13 is set to 0 V. As a result, a high voltage is applied via the thin floating insulating film 19 across the floating gate 11 and source 15. In this condition, by the Fowler-Nordheim tunnel effect, electrons in the floating gate 11 are emitted to the source 15 to thereby erase the data.
In writing data, the drain 16 is set to about 6 V, the source to 0 V, and the control gate 13 to 12 V. In this condition, hot electrons generated near or at the drain 16 are injected into the floating gate 11, to thereby write the data.
In reading data, the drain 16 is set to 1 V, the source 15 to 0 V, and the control gate 13 to 5 V. In this condition, the data "0" or "1" is read which is determined in accordance with whether or not electrons are present in the floating gate 11.
Memory cells described above may also be used in place of memory cells shown in FIG. 11 to form a memory cell array. In this case, the erase lines EL are connected to the sources V.sub.S common for all memory cells. In this arrangement, data can be erased collectively for all memory cells.
In the first conventional technique described above, the stress state of all memory cells is cleared upon collective erase. Therefore, even if write and erase (hereinafter abbreviated as W/E) operations are repeated for example 10.sup.4 times, the stresses will not be accumulated, thereby posing no problem.
However, with a collective erase, data not desired to be erased nevertheless forced to be erased. In this case, the collective erase is not useful and is associated with various difficulties. In order to solve this problem, it may be considered that the memory cell area is divided into a plurality of small sub-areas (hereinafter called blocks) and data is erased on the block unit basis (hereinafter called block erase). In more particular, erase gates of memory cells connected to two word lines are coupled together. In erasing data, one of a plurality of such common erase lines is selected and applied with an erase voltage V.sub.EG =20 V by means of an erase decoder (not shown). In this manner, only memory cells belonging to the selected block can be erased, thus allowing block erase.
Consider the time while a stress is applied to a non-selected cell for the case where cells are divided into blocks. First, consider the stress time with possible erroneous data write (refer to Table 1). This stress time is the same as for collective erase without dividing into blocks. Next, consider the stress time with possible erroneous data erase (refer to Table 1). The maximum stress time under the condition that all blocks (corresponding to 1022 word lines) other than the selected block (corresponding to 2 word lines) repeat W/E operations 10.sup.4 times, is given by EQU 1 ms.times.1022.times.10.sup.4 =10200 seconds
Such a long term stress time may cause erroneous data erase.
The EEPROM in FIGS. 12A to 12C shown as the second conventional example has its memory cell constructed by using only two polysilicon layers so that it is suitable for miniaturization. However, as described above, in block erase, a large stress is applied to the drain of non-selected cells. In addition, the insulating film 19 in particular is as thin as 100 angstroms so that practical block erase is difficult.